In this paper, we investigate the challenges to apply Statistical StaticTiming Analysis (SSTA) in hierarchical design flow, where modules supplied byIP vendors are used to hide design details for IP protection and to reduce thecomplexity of design and verification. For the three basic circuit types,combinational, flip-flop-based and latch-controlled, we propose methods toextract timing models which contain interfacing as well as compressed internalconstraints. Using these compact timing models the runtime of full-chip timinganalysis can be reduced, while circuit details from IP vendors are not exposed.We also propose a method to reconstruct the correlation between modules duringfull-chip timing analysis. This correlation can not be incorporated into timingmodels because it depends on the layout of the corresponding modules in thechip. In addition, we investigate how to apply the extracted timing models withthe reconstructed correlation to evaluate the performance of the completedesign. Experiments demonstrate that using the extracted timing models andreconstructed correlation full-chip timing analysis can be several times fasterthan applying the flattened circuit directly, while the accuracy of statisticaltiming analysis is still well maintained.
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